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[Compress-Decompress algrithms] color_proc333

Description: 基于fpga的MJPEG编码,用硬件描述语言vlogic写的-they simply based on the JPEG coding, using hardware description language to write the vlogic
Platform: | Size: 10059 | Author: xiao | Hits:

[Software Engineering] fpgaJPEGdcode

Description: 基于fpga的JPEG编解码器设计，采用流水线优化解决时间并行性问题，提高DCT/IDCT模块的运行速度。-based fpga JPEG codec design, the flow of time to solve optimization problems in parallel, enhance DCT / IDCT module of the operating speed.
Platform: | Size: 6896091 | Author: Janke | Hits:

[Other resource] djpeg.tar

Description: jpeg格式到bmp格式的硬件实现，verilog开发，fpga 实现。
Platform: | Size: 182053 | Author: 枫叶鹏 | Hits:

[Other resource] fpga-jpeg

Description: jepg verilog example
Platform: | Size: 104097 | Author: 展望 | Hits:

[Other resource] ejpgl-dev-0.251

Description: 嵌入式JPEG Encoder源码，适于PC和FPGA平台，方便移植，该版本为1.20的改进（1.20解压缩后可能无法使用）
Platform: | Size: 163951 | Author: 马振强 | Hits:

[Other resource] fpgajpeg

Description: 基于FPGA的JPEG图像压缩芯片设计
Platform: | Size: 103672 | Author: 李飞 | Hits:

[Other resource] huffman

Description: 用于FPGA的huffman算法的HDL编码，包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。
Platform: | Size: 10891 | Author: caesar | Hits:

[Other resource] quant

Description: 用于FPGA的量化算法的HDL编码，包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。
Platform: | Size: 14647 | Author: caesar | Hits:

[Other resource] iquant

Description: 用于FPGA的反量化算法的HDL编码，包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。
Platform: | Size: 13343 | Author: caesar | Hits:

[Other resource] rle

Description: 用于FPGA的变长编码算法的HDL编码，包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。
Platform: | Size: 4581 | Author: caesar | Hits:

[Other resource] zigzag

Description: 用于FPGA的Z变化算法的HDL编码，包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。
Platform: | Size: 7571 | Author: caesar | Hits:

[Other resource] zigzag_decode

Description: 用于FPGA的反Z变换算法的Verilog代码。可用于JPEG及MPEG压缩算法。
Platform: | Size: 3739 | Author: caesar | Hits:

[VHDL-FPGA-Verilog] 用FPGA实现JPEG的Verilog源代码

Description:
Platform: | Size: 226360 | Author: sb_6316773 | Hits:

[Graph program] libj2k.tar

Description: JPEG2000压缩解压程序-JPEG2000 compression decompression procedures
Platform: | Size: 28672 | Author: subspace | Hits:

[VHDL-FPGA-Verilog] MSP430C

Description: 用FPGA实现JPEG的Verilog源代码-JPEG with the FPGA implementation of the Verilog source code
Platform: | Size: 750592 | Author: 杜晓伟 | Hits:

[File Format] JRthesis

Description: JPEG Image Compression Using an FPGA
Platform: | Size: 1044480 | Author: khurram | Hits:

[VHDL-FPGA-Verilog] jpeg_hardware.tar

Description: 用FPGA实现的JPEG压缩器，可以直接使用，内含完整文档说明-This project features a complete JPEG Hardware Compressor (standard Baseline DCT, JFIF header) with 2:1:1 subsampling, able to compress at a rate of up to 24 images per second at the maximum resolution 352x288 (on XC2V1000-4 @ 40 MHz). IMAGE RESOLUTION IS LIMITED TO 352x288. It takes an RGB input (row-wise) and outputs to a memory the compressed JPEG image with headers. A testbench has been made that takes a bitmap image from your computer and writes a compressed JPEG file by simulating the code. In order to be able to run the project you must first generate the RAM/ROM cores and the DCT2D core with Xilinx CoreGen. The configuration values are listed at the bottom of the file compressor.vhd. If you run into any problems downloading the files from the cvs please check that you are downloading them in binary form. For any questions my email is: victor.lopez [(at)] ono [(dot)] com PLEASE NOTICE THAT THIS CORE IS LICENSED UNDER http://creativecommons.org/licenses/by-nc-sa/3.0/ (Creative Co
Platform: | Size: 868352 | Author: | Hits:

[VHDL-FPGA-Verilog] mkjpeg.tar

Description: 用FPGA实现的JPEG编码器，可以直接使用，内含完成说明文档，经过验证无误。-• JPEG baseline encoding JPEG ITU-T T.81 | ISO/IEC 10918-1 • Standard JFIF header v 1.01 automatic generation • Color images only (3 components, RGB 24 or 16 bit, YUV input) • Two programmable Quantization tables • Hardcoded Huffman tables (luminance and chrominance) • 2.3 to 2.7 clock cycles per one input 24 bit pixel @ 50 Quality • OPB programming and data Host interface • 4:2:2 subsampling • Source code target independent, synthesizable RTL VHDL code • Detailed documentation
Platform: | Size: 21650432 | Author: | Hits:

[Windows Develop] fFPGA_imagep

Description: fpga实现图像处理，JPEG标准下图象压缩，VVHDL语言编程。 ， -fpga image processing to the JPEG standard for image compression, VVHDL language programming. And
Platform: | Size: 296960 | Author: 明白的 | Hits:

[Other] image-compression

Description: 实现jpeg图像压缩，基于FPGA的JPEG图像压缩算法实现 基于FPGA的JPEG图像压缩系统的实现(Image compression of JPEG based on MATLAB， 实现jpeg图像压缩，基于FPGA的JPEG图像压缩算法实现 基于FPGA的JPEG图像压缩系统的实现 JPEG image compression, JPEG image compression algorithm based on FPGA implementation of FPGA based JPEG image compression system)
Platform: | Size: 71680 | Author: zyz10 | Hits:
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